| NO OPT & CPT VISA'S
Hello, My name is Mahitha and I am a Staffing Specialist at Veda Info Inc. I am reaching out to you on an exciting job opportunity with one of our clients. Please find the JD below and kindly respond with the below details if interested: Job Title:- Design verification Engineer Work Location: Mountain View, CA (Initial Remote) Contract duration: Long Term Type: Fulltime/W2
Does this position require Visa independent candidates only? No Job Details:- JD Key words Design verification UVM Low power ARM , AXI, APB, AHB .. UPF Gate Level Simulation GLS At least 7-8 years of experience with pre-silicon DV. Knowledge and hands on experience with Verilog, System Verilog , UVM, debugging waveforms . Must be proficient with : building a testbench for a medium complexity block using System Verilog and UVM . Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM. Developing, maintaining and supporting of the UVM verification environment. Debugging tests with design engineers to deliver functionally correct design blocks . OOPS, randomization, constraints, interfaces ◦ writing & analyzing functional coverage, assertions . Generating and analyzing code coverage
Warm regards, Mahitha Technical Recruiter Office: 310-929-1616 EXT: 122 Ph: 310-7331198 E-Mail: mahitha@vedainfo.com Vedainfo Inc., Website: www.vedainfo.com | 
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